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(R)
XC7336 36-Macrocell CMOS EPLD
Product Specifications
Features
* Ultra high-performance EPLD - 5 ns pin-to-pin speed on all fast inputs - 167 MHz maximum clock frequency
interconnected by the 100%-populated Universal Interconnect Matrix (UIMTM ). Each Fast Function Block has 24 inputs and contains nine Macrocells configurable for registered or combinational logic. The nine Macrocell outputs feed back to the UIM and can simultaneously drive the output pads. The UIM allows 100% connectivity between all function blocks and input pins, providing the ability to utilize 100% of the device while eliminating routing issues. The XC7336 is designed in 0.8 CMOS EPROM technology, in speed grades ranging from 5 to15 ns. The XC7336Q is also available now, providing lower power consumption in -10, -12 and -15 ns speed grades. Device logic is automatically configured to the user's specifications using the XEPLD software. The XEPLD software is capable of optimizing and collapsing logic. The SMARTswitch software/hardware feature allows implementation of buried combinatorial logic functions in the UIM, thus increasing device utilization. The XEPLD software supports third party schematic capture and HDL entry tools, as well as direct equation-based text files. Using a workstation or PC platform, designs are automatically mapped into the XC7336 in a matter of minutes.
* New low power XC7336Q * 100% routable with 100% utilization * Incorporates four PAL-like 24V9 Fast Function Blocks * 36 Output Macrocells - Programmable I/O architecture - 24 mA drive * High-performance P compatible * Peripheral Component Interface (PCI) compatible * JEDEC standard 3.3 V or 5 V I/O operation * Multiple security bits for design protection * 44-pin leaded chip carrier and 44-pin quad flat pack packages
General Description
The XC7336 is a member of the Xilinx XC7300 EPLD family. It consists of four PAL-like 24V9 Fast Function Blocks
PQ44 PC44
PC44
PQ44
22
28
I/FI
19 12 FFB1 34 12 FFB2
15
I/FI
42
36
1 2 3 5 6 7 8 9 10
7 8 9 11 12 13 14 15 16
I/FO/FI I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO
MC1-1 MC1-2 AND ARRAY MC1-3 MC1-4 MC1-5 MC1-6 MC1-7 MC1-8 MC1-9 9 12 12 3 12 AND ARRAY 12 3
MC2-9 MC2-8 MC2-7 MC2-6 MC2-5 MC2-4 MC2-3 MC2-2 MC2-1 9
I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO FO/FOE1
9
9
29 30 33 34 35 36 37 38 39
23 24 27 28 29 30 31 32 33
12 FFB4
UIM
12 FFB3 MC3-9 FO/FOE0 I/FO/FI I/FO/FI I/FO/FI/MR I/FO/FI I/FO/FI I/FO/FI FO/FCLK0 FO/FCLK1 12 AND ARRAY 12 3 MC3-8 MC3-7 MC3-6 MC3-5 MC3-4 MC3-3 MC3-2 MC3-1 9
X5452
21 20 19 18 16 14 13 12 11
27 26 25 24 22 20 19 18 17
I/FO I/FO I/FO I/FO I/FO I/FO/FI I/FO/FI I/FO/FI I/FO
MC4-1 MC4-2 MC4-4 MC4-5 MC4-6 MC4-7 MC4-8 MC4-9 9 AND ARRAY MC4-3 12 12 3
9
9
40 43 44 1 2 3 4 5 6
34 37 38 39 40 41 42 43 44
Figure 1. XC7336 Functional Block Diagram
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XC7336 CMOS EPLD
Fast Function Blocks (FFB) The XC7336 provides four Fast Function Blocks which have 24 inputs that can be individually selected from the UIM, 12 fast input pins, or the 9 Macrocell feedbacks from the Function Block. The programmable AND array in each Fast Function Block generates 45 product terms to drive nine Macrocells in each FFB. Each Macrocell (Figure 2), can be configured for registered or combinatorial logic. Five product terms from the programmable AND array are allocated to each Macrocell. Four of these product terms are ORed together and may be optionally inverted before driving the input of a programmable D-type flip-flop. The fifth product term drives the asynchronous active-High programmable Reset or Set Input to the Macrocell flipflop. The flip-flop can be configured as a D-type or Toggle flip-flop or transparent for combinatorial outputs. The programmable clock source is one of two global FastCLK signals (FCLK0 or FCLK1) that are distributed with short delay and minimal skew over the entire chip. I/O Block The Fast Function Block Macrocells drive chip outputs directly through 3-state output buffers. Each output buffer can be individually controlled by one of two dedicated active-High Fast Output Enable inputs or permanently
enabled or disabled. The Macrocell output can also be routed back as an input to the Fast Function Block, and the UIM.
Power-On Characteristics/Master Reset
The XC7336 device undergoes a short internal initialization sequence upon device powerup. During this time (tRESET), the outputs remain 3-stated while the device is configured from its internal EPROM array and all registers are initialized. If the MR pin is tied to VCCINT, the initialization sequence is completely transparent to the user and is completed in tRESET after VCCINT has reached 4.75 V. If MR is held low while the device is powering up, the internal initialization sequence begins and outputs will remain 3-stated until the sequence is complete and MR is brought High. VCC rise must be monotonic to insure the initialization sequence is performed correctly. For additional flexibility, the MR pin is provided so the EPLD can be reinitialized after power is applied. On the falling edge of MR, all outputs become 3-stated and the initialization sequence is started. The outputs will remain 3-stated until the internal initialization sequence is complete and MR is brought High. The minimum MR pulse width is tWMR. If MR is brought High after tWMR, but before tRESET, the outputs will become active after tRESET.
2 Global Fast OE 12 from Fast Input Pins
2 AND Array
12
24 Inputs from UIM
3
Sum-of-Products from Previous Macrocell 9 from FFB Macrocell Feedback 5 9 5 Private P-Terms per Macrocell
Fast Clocks 01
I/O Block 1 of 9 Macrocells OE Control
0 1
D/T Q Output Polarity S/R
I/O Pin
P-Term Assignment Control Feedback to UIM Sum-of-Products to Succeeding Macrocell Pin Feedback to UIM
Register Transparent Control
X5218
Figure 2. Fast Function Block and Macrocell Schematic
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From Previous Macrocell Single-Product Term Assignment
Fast Function Block. Each UIM input can be programmed to connect to any UIM output. The delay through the interconnect matrix is constant. When multiple inputs are programmed to be connected to the same output, this output produces the logical AND of the input signals. By choosing the appropriate signal polarities at the input pins, Macrocell outputs and Fast Function Block AND-array inputs, this AND logic can also be used to implement wide NAND, OR or NOR functions. This offers an additional level of logic without additional speed penalty.
D/T
4
Q
Output Polarity
3.3 V or 5 V Interface Configuration
Eight-Product Term Assignment
S/R D/T Q
4
The XC7336 can be used in systems with two different supply voltages: 3.3 V and 5 V. Each XC7336 device has separate VCC connections to the internal logic (VCCINT) and to the I/O pads (VCCIO). VCCINT must always be connected to a 5 V supply. VCCIO may be connected to either 3.3 V or 5 V, depending on the output interface requirement. When VCCIO is connected to 5 V, the input thresholds are TTL levels, and thus compatible with 3.3 V and 5 V logic. The output High levels are also TTL compatible. When VCCIO is connected to 3.3 V, the input thresholds are still TTL levels, and the outputs pull up to the 3.3 V. This makes the XC7336 ideal for interfacing directly to 3.3 V components. In addition, the output structure is designed so that the I/O can also safely interface to a mixed 3.3 V and 5 V bus simultaneously. Low Power (Q) Devices The XC7336-10, -12 and -15 are available in a low power variant, designated the XC7336Q. Timing parameters for the XC7336 and the XC7336Q devices are identical. However, the XC7336Q features much lower power consumption. Using the XC7336Q will prove advantageous to any system design where power consumption and EM emissions are critical system parameters.
Output Polarity
X3374
Figure 3. Fast Function Block Product Term Assignment
Product Term Assignment Each Macrocell sum-of-product OR gate can be expanded using the Export product-term assignment feature. The Export function transfers product-terms in increments of four from one Macrocell to the neighboring Macrocell (Figure 3). Complex logic functions requiring up to 36 product-terms can be implemented using all nine Macrocells within the Fast Function Block. When productterms are assigned to adjacent Macrocells, the productterm normally dedicated to the Set or Reset function becomes the input to the Macrocell register. Universal Interconnect Matrix The UIM receives input from Macrocell outputs, I/O pins, and dedicated input pins. Acting as an unrestricted crossbar switch, the UIM generates 24 output signals to each
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XC7336 CMOS EPLD
Power Management
The XC7336 features a power-management scheme which permits non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often reduced significantly, since, in most systems only a few paths are speed critical. Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral description. To minimize power dissipation, unused Function Blocks are turned off and unused Macrocells in used Function Blocks are configured for low power operation. Operating current for each design can be approximated for specific operating conditions using the following equation: For non-Q devices: ICC(mA) = MCHP (4.3) + MCLP (3.5) + MC (0.005 mA/MHz) f For Q devices: (-10, -12, -15): ICC (mA) = MCHP (2.0) + MCLP (1.6) + MC (0.005 nA/MHz) f Where: MCHP = MCLP = MC = f = Macrocells in high-performance mode Macrocells in low-power mode Total number of Macrocells used Clock frequency (MHz)
Design Security
The XC7336 has a multibit security system that controls access to the configuration programmed into the device. This security scheme uses multiple EPROM bits at various locations within the EPROM array to offer a higher degree of design security than other EPROM and fusedbased devices.
Prototyping and Programming
Xilinx offers the HW-120 programmer for use during prototyping as well as support from major third party programmer companies. For production volumes, Xilinx and their licensed distributors offer factory programming of the XC7336 devices. For factory programming procedures, contact your local Xilinx representative.
XEPLD Translator Software
The designer can create, implement, and verify digital logic circuits for EPLD devices using the Xilinx XEPLD software. Designs can be represented as schematics consisting of XEPLD library components, as behavioral descriptions (Boolean, HDL etc.), or as a combination of both techniques. The XEPLD translator automatically optimizes, collapses, and implements the design as well as writing a programming file without user intervention. At the completion of the compilation process, the XEPLD translator writes detailed report files for design analysis and documentation.
Figure 4 shows a typical power calculation for the XC7336 device, programmed as two 16-bit counters and operating at the indicated clock frequency.
200
High Perform ance
150 Typical ICC (mA)
Low Power
100
High Pe rforman
ce
50
s Q device er Low Pow
0
50 Clock Frequency (MHz)
100
X5767
Figure 4. Typical ICC vs Frequency for XC7336
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Here are just a few of the XEPLD Development System features: * Automatic Optimization and Mapping Designs are automatically minimized and mapped into the devices for optimal efficiency and high performance. Critical logic functions are automatially assigned to special resources such as high speed clocks and global output enable signals. This allows the user to concentrate on design functionality without concern for physical implementation
* N-to-1 PAL Conversion Utility XEPLD automatically combines 20- and 24-pin standard PAL files into one top-level design file, checks for errors, and compiles the design into one or more EPLDs. The N-to-1 PAL converter is ideal for one step logic consolidation and board space reduction. * Complete Design Control Users have the option to override the automatic features of XEPLD and selectively control any or all device resources. * Multiple Platform Support XEPLD runs on IBM Compatible PCs, Sun, HP700, and IBM RS6000 platforms.
* Automatic use of UIM Resources - SMARTswitch The Universal Interconnect Maticx (UIM) used in Xilinx EPLDs provides an additional level of logic at no additional delay. XEPLD automatically uses the inherent logic capability of the UIM when possible to reduce Macrocell requirements and increase speed.
Notice: The information contained in this data sheet pertains to products in the initial production phases of development. These specifications are subject to change without notice. Verify with your local Xilinx sales office that you have the latest data sheet before finalizing a design.
Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +250 Units V V V C C
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operating Conditions
Symbol VCCINT/ VCCIO VCCIO VIL VIH VO TIN Parameter Supply voltage relative to GND Supply voltage relative to GND Supply voltage relative to GND I/O supply voltage relative to GND Low-level input voltage High-level input voltage Output voltage Input signal transition time Commercial Industrial Military TA = TA = 0 C to 70 C TA = -40oC to 85oC -55oC to TC = +125oC
o o
Min 4.75 4.50 4.50 3.0 0 2.00 0
Max 5.25 5.50 5.50 3.60 0.80 VCC +0.5 VCCIO 50
Units V V V V V V V ns
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XC7336 CMOS EPLD
DC Characteristics Over Recommended Operating Conditions
Symbol Parameter 5 V TTL High-level output voltage VOH 3.3 V High-level output voltage 5 V TTL Low-level output voltage VOL 3.3 V Low-level output voltage IIL IOZ CIN CIN COUT1 Input leakage current Output high-Z leakage current Input capacitance for Input and I/O pins Input capacitance for global control pins (FCLK0, FCLK1, FOE0, FOE1) Output capacitance (Non-Q) ICC2 Supply current (Q) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 24 mA VCC = Min VCC = Max VIN = GND or VCCIO VCC = Max VIN = GND or VCCIO VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = VCC or GND VCCOUT = VCCCO= 5V f = 1.0 MHz @ 25C Min 2.4 2.4 0.5 0.4 10.0 10.0 6.0 8.0 10.0 126 Typ mA 55 Typ Max Units V V V V A A pF pF pF
Preliminary
Power-up/Reset Timing Parameters
Symbol tWMR tRESET Notes: Parameter Master Reset input Low pulse width Configuration completion time Min 100 80 160 Typ Max Units ns s
1. Sample tested. 2. Measured with device programmed as two 16-bit counters.
tWMR MR tRESET Output Hi-Z
X5349
Figure 5. Global Reset Waveform
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Fast Function Block (FFB) External AC Characteristics3
XC7336-5 Symbol Parameter Min tPD tSU tH tCO tFOE tFOD fMAX tWLH Notes: Fast input to output valid 4 I/O or input to output valid 4 Fast input setup time before FCLK I/O or input setup time before FCLK Fast, I/O or input hold time after FCLK FCLK input to output valid FOE input to output valid FOE input to output disable Max count frequency 4 Fast Clock pulse width Max 5.0 8.5 4.5 7.0 0 4.5 7.0 7.0 167.0 3.0 125.0 4.0 5.0 8.5 0 4.5 7.5 7.5 100.0 5.0 Min Max 7.5 12.0 5.0 10.0 0 8.0 10.0 10.0 80.0 5.5 Min Max 10.0 15.0 6.0 13.0 0 9.0 12.0 12.0 66.7 6.0 Min Max 12.0 19.0 7.0 15.0 0 12.0 15.0 15.0 Min Max 15.0 23.0 ns ns ns ns ns ns ns ns MHz ns XC7336-7 XC7336-10 XC7336-12 XC7336-15 Units
3. All appropriate ac specifications tested using Figure 7 as test load circuit. 4. Assumes four product terms per output.
Fast Input tSU FCLK tCO Output Output tH FOE Pin tFOD tFOE
Input or I/O tSU FCLK tCO Output
X5695
tH FCLK
tWH
tWL
Figure 6. Switching Waveforms
VTEST
R1
Device Output
Test Point
R2 Device Input Rise and Fall Times < 3ns
CL
VCCIO Level 5V 3.3 V
VTEST 5.0 V 3.3 V
R1 160 260
R2 120 360
CL 35 pF 35 pF
X5222
Figure 7. AC Load Circuit
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XC7336 CMOS EPLD
FOE
tFOE
FAST INPUT
tIN Fast Function Block UIM Delay tUIM FFB Logic tFLOGI P-Term Assignment tPTXI FFB Feedback tFFD tFSUI tFCOI tFPDI tFHI tFAOI
I, I/O
tIN
tFOUT
Pin
FCLK
tFCLKI
X5221
Figure 8. XC7336 Timing Model
Timing Model Timing within the XC7336 is accurately determined using external timing parameters from the device data sheet, using a variety of CAE simulators, or with the timing model shown in Figure 8.
The timing model is based on the fixed internal delays of the XC7336 architecture which consists of three basic parts: I/O Blocks, the UIM and Fast Function Blocks. The timing model identifies the internal delay paths and their relationships to ac characteristics. Using this model and the ac characteristics, designers can easily calculate the timing information for the XC7336.
Fast Function Block (FFB) Internal AC Characteristics
XC7336-5 Symbol Parameter tFLOGI tFSUI tFHI tFCOI tFPDI tFAOI tPTXI tFFD FFB logic array delay 5 FFB register setup time FFB register hold time FFB register clock-to-output delay FFB register pass through delay FFB register async. set delay FFB p-term assignment delay FFB feedback delay 2.5 1.0 1.0 0.5 2.0 0.6 0.5 tFLOGILP Low-power FFB logic array delay 5 Min Max 1.0 2.0 1.5 2.5 1.0 0.5 2.0 0.8 4.0 XC7336-7 Min Max 1.5 3.5 2.5 2.5 1.0 0.5 2.5 1.0 5.0 XC7336-10 Min Max 1.5 5.5 3.0 3.0 1.0 1.0 3.0 1.2 6.5 XC7336-12 Min Max 2.0 7.0 4.0 3.0 1.0 1.0 4.0 1.5 8.0 XC7336-15 Min Max Units 2.0 8.0 ns ns ns ns ns ns ns ns ns
Notes: 5. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell.
Internal AC Characteristics
XC7336-5 Symbol Parameter tIN tFOUT tUIM tFCLKI Input pad and buffer delay FFB output buffer and pad delay Universal Interconnect Matrix delay Fast clock buffer delay Min Max 1.5 2.0 3.5 1.5 XC7336-7 Min Max 2.5 3.0 4.5 1.5 XC7336-10 Min Max 3.5 4.5 5.0 2.5 XC7336-12 Min Max 4.0 5.0 7.0 3.0 XC7336-15 Min Max 5.0 7.0 8.0 4.0 Units ns ns ns ns
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Combinatorial Switching Characteristics
tIN
Input, I/O Pin tUIM UIM Delay tLOGI tFLOGI Logic Delay tPTXI P-Term Assignment Delay tPDI tFPDI Transparent Register Delay tOUT tFOUT Output Buffer
Output Pin
X3339
Asynchronous Clock Switching Characteristics
tPCW tPCW
Input, I/O Pin tIN Input, I/O Delay tUIM UIM Delay tLOGI Clock at Register tSUI tHI Data from Logic Array tCOI Register to UIM tOUT Register to Output Pin
X3580
tUIM
tAOI
tUIM
tOUT
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XC7336 CMOS EPLD
Synchronous Clock Switching Characteristics
tCWF tCWF
FCLK Pin tSUIN tSUCEIN Data/CE at Input I/O Register tCOIN tUIM Input, I/O Register to UIM tFCLKI Fast Clock Input Delay tIN tUIM Data at Input I/O Pin tLOGI tFLOGI Data at Input Register tCOI tFCOI Register to Output Pin
X3494
tHIN tHCEIN
tSUI tFSUI
tHI tFHI
tOUT tFOUT
XC7336 Pinouts
PQ44 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PC44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Input I/FO/FI I/FO/FI I/FO/FI I/FO/FI FO/FCLK0 FO/FCLK1 I/FO/FI I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO/FI I/FO/FI I/FO/FI VCCINT I/FO MC4-5 XC7336 MR Output MC3-6 MC3-5 MC3-4 MC3-3 MC3-2 MC3-1 MC1-1 MC1-2 MC1-3 MC1-4 MC1-5 MC1-6 MC1-7 MC1-8 MC1-9 MC4-9 MC4-8 MC4-7 MC4-6 PQ44 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PC44 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Input I/FO I/FO I/FO I/FO I/FI I/FO I/FO GND VCCIO I/FO I/FO I/FO I/FO I/FO I/FO FO/FOE1 FO/FOE0 VCCINT/VPP I/FI I/FO/FI I/FO/FI MC3-8 MC3-7 MC2-7 MC2-6 MC2-5 MC2-4 MC2-3 MC2-2 MC2-1 MC3-9 XC7336 GND MC4-4 MC4-3 MC4-2 MC4-1 MC2-9 MC2-8 Output
GND
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Ordering Information
XC7336
Device Type Power Option Speed
- 5 PC 44 C
Temperature Range Number of Pins Package Type
Power Options Q Low Power -10, -12, -15 speeds Speed Options -15 15 ns pin-to-pin delay -12 12 ns pin-to-pin delay -10 10 ns pin-to-pin delay -7 7.5 ns pin-to-pin delay (commercial only) -5 5 ns pin-to-pin delay (commercial only) Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier WC44 44-Pin Windowed Ceramic Leaded Chip Carrier PQ44 44-Pin Plastic Quad Flat Pack Temperature Options C Commercial I Industrial
0oC to70oC -40oC to 85oC
Component Availability
Pins Type Code -15 -12 XC7336 -10 -7 -5 44 Plastic Ceramic Plastic PLCC CLCC PQFP PC44 CI CI CI C C WC44 CI CI CI C C PQ44 C C C C C I = Industrial = -40 to 85C
X5650
68 Plastic PLCC PC68
84
100
144
160 Plastic PQFP PQ160
225 Plastic Windowed BGA BGA BG225 WB225
Ceramic Plastic Ceramic CLCC PLCC CLCC WC68 PC84 WC84
Plastic Ceramic PQFP PGA PQ100 PG144
C = Commercial = 0 to +70C
(R)
The Programmable Logic Company
SM
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XC7336 CMOS EPLD
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